Integrated Circuit. Transistor Transistor Logic (TTL). 4−Line−to−16−Line Decoder /Demultiplexer. 24−Lead DIP Type Package. Description: The NTE is a. 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test . datasheet, circuit, data sheet: NSC – 4-Line to Line for Electronic Components and Semiconductors, integrated circuits, diodes, triacs.

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(PDF) 74154 Datasheet download

Since the ouputs are active low, NAND gates do the job. Why are the outputs inverted?

That is, if the outputs were active high, OR gates would perform the synthesis desired. These demultiplexers are ideally suited for implementing high-performance memory decoders. This allows more flexibility in the logic functions available. Sign up or log in Sign up using Google. This chip is often used in demultiplexing applications, such as digital clocks, LED matrices, and other graphical outputs.

The active-low output is just how the design for that specific decoder was carried out – there is also active-high varieties. Home Datwsheet Tags Users Unanswered. The active-low enable inputs allow cascading of demultiplexers over many bits. Inputs were pulled high by default, and only pulled low when necessary, to save power.

National Semiconductor

WhatRoughBeast 49k 2 28 I have a doubt in the demultiplexer section. High speed signals were usually active low, for much the same reason. Email Required, but never shown. If you want to know exactly what is going on then draw out the truth table, but it is unlikely their function will make much sense to you.


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My first question is more important However, due to the internal structure of theonly one output can be enabled at a time. Rather than providing only a single enable, both pins are used. Is the hardware implementation circuit different than the one explained in theory? Sign up or log in Sign up using Google. This all has to do with the actual ic design. So you can use a 47 kilohm resistor to pull up drops 1. That is, for an input ofthe 0 output is selected, and it is driven low.

And that’s what is going on with the All the other ouputs stay high. The datasheet of these components is always the key to the correct implementation.

First, the inversion of the outputs simply means that the output is active low. Sign up using Email and Password.

Common collector, with the signal connected to the emitter, which remains at 0. This is the image of a 1 to 16 demux. And why are there 2 of them, you adtasheet Each or these 4-line-toline decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low.


National Semiconductor – datasheet pdf

Will someone please explain the purpose of inverting the outputs 0 through 15 as well as the use datashewt NAND gates here?

I am a new user so I didn’t know I had that power. According to the internal logic diagram on the datasheet, the G inputs are connected to a two-input AND gate with inverting inputs, whose output feeds one input of all the NAND gates that produce the outputs.

But when we try to implement a demultiplexer using a TTLthis is the truth table that is given in the book:. Sign up using Facebook. So they are inverted a explained in the theory.

Understand, this is a typical example of application, not it’s sole purpose. The person who took time to answer the question will appreciate that. When either strobe input is high, all outputs are high.

The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input low.