Implementation of Cordic Algorithm for FPGA. Based Computers Using Verilog. pani1, ju, a3. The CORDIC rotator seeks to reduce the angle to zero by rotating the vector. To compute . See the description of the CORDIC algorithm for details. */ module. Tags: verilog code for cordic algorithm verilog code for vector verilog code for .. specific device designations, other words log Abstract.. code in the example.
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The floating point numbers are represented as integers. Both the sine and the cosine of algorthm input angle will be computed. The interface of the module looks as follows:. We will first write a unit test for the design. Veripog idea is to use berilog cos and sin functions from the math module to compute the expected results on a number of input angles, and to compare them with the outputs from the design under test.
Here is the code:. As the design will perform its calculations in finite precision, there will be rounding errors. Therefore, the comparisons between expected and actual results are performed using an error margin. We may want to use the test bench for designs with different characteristics; therefore, the error margin is made a parameter.
The precision is specified in algorighm of the number of bits after the point, using the parameter fractionSize. To represent the numbers, we use the intbv class, which is basically an integer-like type with bit-vector capabilities. Note that we constrain the intbv instances by specifying the range of valid integer values, not by a bit width.
For high-level, algorithmic work, this is much easier. Moreover, it enables fine-grained range error checking at run-time. By filling in the parameters of the bench function, we can construct an actual veeilog bench that runs a simulation, as follows:. To implement the design, we will use the Cordic algorithm, a very popular algorithm to compute trigonometric functions in hardware.
On this page, we are mainly interested in the mechanical characteristics of the algorithm and their hardware implications. For more information and background on the algorithm itself, please consult other sources, such as this paper by Ray Andraka. The Cordic algorithm is an iterative algorithm based on vector on over elementary angles.
The algorithm normally operates in one of two modes.
Computing sin & cos in hardware with synthesisable Verilog
In rotation mode, it rotates a vector x 0algorithmm 0 in the Cartesian plane over an input angle z 0. The Cordic equations for this mode are:. These equations can be implemented with relatively simple hardware. This is the characteristic that makes the Cordic algorithm attractive. In particular, multiplications with a factor 2 -i are simply shift-right operations.
Also, the arctangent values tan -i 2 -i can be precomputed and slgorithm in a small look-up table. The Cordic equations can be used for a variety of computations. For our purposes, it can be shown that.
The Cordic algorithm can be implemented in many ways, with various characteristics and advantages. On this page, we will implement a parallel, iterative processor, which is a fairly straightforward mapping of the equations into a bit-parallel data path and a state machine. The actual computation is done by the processor generator.
Note that algorothm the generator function, we calculate some data such as the X0 vordic, and the look-up table of elementary arctangents, represented by the angles tuple. The internal number variables are represented by intbv instances.
Computing sin & cos in hardware with synthesisable Verilog
The dual nature of this class comes corrdic very handy. On the one hand, we can constrain the instances as integer subtypes by specifying the valid integer range at construction time. On the other hand, we can access their two’s complement representation as a bit vector, for example for slicing or right-shifting.
It seems obvious that a type that unifies the integer and the bit vector views should be very useful for hardware design. One would therefore expect a similar feature in other HDLs.
Other HDLs seem to try to solve the issues by creating more and more integer and bit-vector like types. In MyHDL, a single type does it all – the intbv class. Now that we have a working design and only now! For example, consider the instantiation of the design under test in the test bench:. As before, the dut object is a simulatable design instance, coedic as a side effect of the instantiation, an equivalent Verilog module file will be generated.
The Verilog output is as follows:. It is important to realize that the conversion occurs on a design instance. This means that the code has already been elaborated by the Python interpreter.
Therefore, the convertor works on the simulatable data structure, which is a hierarchical list of generators. This means that only the source code of generator functions is converted.
The pleasant consequence is that the restrictions of the “convertible subset” apply only to the code inside generator functions, not to any code outside them.
For example, consider how the look-up table of elementary arctangents is algorthm up in the SineComputer design:. This line uses things like a list comprehension and a call to the trigonometric function atan from the math library, At this point, this is beyond the scope of the convertible subset, and it may stay like that forever.
But as this code is outside a generator function, it doesn’t matter. This is just fine for the convertor.
Note how this single-line lookup is expanded into a case statement in the Verilog output. Note that we have been talking about the convertible subset, and not about the “synthesizable subset”. The reason is that the convertible subset is much less restrictive. You can find more information about the convertible subset in the MyHDL manual.
Obviously, MyHDL code intended for synthesis also has to take synthesis-related restrictions into account. But again, these restrictions only apply to the code inside generator functions, because only that code is actually converted.
The described behavior is a unique feature of the MyHDL design flow. Outside generator functions, you can use Python’s full power to describe designs. As long as the code inside them obeys the constraints of the convertible subset, the design instance can always be converted to Verilog. And if that code also obeys the constraints of the synthesizable subset, the result will be synthesizable Verilog.
One important feature of the convertor is that it handles the details of signed and unsigned representations automatically. When writing synthesizable code, a MyHDL designer can use a high-level view for integer operations by using the intbv type, and rely on the underlying two’s complement representation to do the right thing automatically.
In contrast, a Verilog designer is forced to deal with low-level representational issues explicitly. This can become very tricky, especially with negative numbers and the signed representation.
First of all, note in jn Verilog output that the convertor infers which variables have to be declared as signed. This is the easy part. I believe it’s quite clear what this is supposed to do. With the underlying two’s complement representation, it works dordic positive and negative values of y. The convertor has to deal with several potential pitfalls. The fundamental problem is that Verilog uses an apgorithm interpretation by default, which is the opposite from what you should do to verolog the naturally algorithmm results.
Otherwise, Verilog will interprete all operands in a mixed expression as unsigned. Having said that, the Verilog literature seems to indicate that a shift operation is an exception to this rule. But the convertor doesn’t take risks and inserts the typecast as a general measure.
It may be redundant in this case. Actually, I would have expected that this typecast would not be necessary – after all, we are shifting a signed number. However, my current simulator Cver tells me that it is. It may be wrong, I don’t know.
Anyway, the cast is an additional safety net. The message you should get from this discussion is the following: I believe that writing the code in a natural, high-level way in MyHDL, and letting the convertor take care of the low-level veeilog issues, is a better option.
Of course, we crodic need to make sure that the convertor gets it right, which is hard enough. Clearly we will want to verify that the Verilog output coreic the convertor is correct. To set up a co-simulation, we need to create a Cosimulation object for the Verilog design. The Verilog convertor makes this task easier. In addition to the Verilog code for the design itself, it also generates a Verilog test bench stub that defines an interface between the Verilog design and a Cosimulation object. We start by doing the Verilog conversion itself first.
Then, we define the command to start up the Verilog simulator. This is of course simulator-specific. The command shown is for the open-source Cver simulator. It loads a vpi module that defines the interface between the MyHDL simulator algorthm the Verilog simulator. Also, both the Verilog code for the design and the test bench xlgorithm are compiled. The Cosimulation object is then constructed with the command as its first parameter, followed by a number of keyword arguments.
The keyword arguments make the link between signal names declared in the Verilog test bench stub and signals in the MyHDL code. When the signal names in MyHDL and Verilog are identical we can use a little trick and simply pass the local namespace dictionary locals to the constructor.
It turned out that the handling of signed variables with shift operations had not been implemented and tested properly. Therefore, this example has been the trigger to fix these bugs and develop MyHDL 0.